This invention relates to integrated circuit (“IC”) structures. More particularly, this invention relates to decreasing soft errors and cell leakage in IC structures.
When alpha or neutron particles penetrate the silicon of an IC (e.g., due to atmospheric radiation or similar causes), some particles collide with silicon atoms and generate electrical charges. For instance, charges can be generated in the depletion region of an IC structure. Alpha particles can create an extended depletion region along its track, known as a funneling region. Charges generated in the funneling region can be collected in a node of the IC structure. Charges can also be generated outside the depletion region and diffuse to the depletion region of the node. In addition, the collision of neutron particles with silicon atoms can trigger reactions that lead to the emission of alpha particles, which can in turn lead to further charge generation. The resulting charges can alter a voltage of an IC structure, a phenomenon often referred to as a soft error or single event upset.
Soft errors are especially significant when they occur in memory cells. The information stored by a node of a memory cell may be corrupted or reversed in polarity as a result of the soft error. This corruption can lead to improper operation of an IC or system that uses the memory. IC memories become more susceptible to soft errors as the transistors used in such memories become smaller. In addition, smaller transistors can lead to greater cell leakage.
Several approaches have been taken to make IC structures less susceptible to soft errors. These approaches often make use of thin-film transistors (“TFTs”). For instance, one known approach uses TFTs for the pull-up transistors of memory cells, with a metal dielectric. Bulk silicon transistors are used for pull-down transistors and pass-gates. Unfortunately, memory cells employing this approach are still susceptible to soft errors due to the partial use of bulk silicon transistors. In addition, metal dielectrics are typically thick (e.g., several tenths of a micron), resulting in either weak gate drive or larger devices.
Another approach employs TFTs in a way designed to optimize IC performance. Aluminum oxide is used as the dielectric material, resulting in a very high dielectric constant “K.” Unfortunately, such cells require ultra-low-temperature fabrication techniques that are typically not available among standard complementary metal-oxide semiconductor (“CMOS”) processes. In addition, such transistors tend to be relatively large, making them undesirable for memories with a relatively large number of cells.
In view of the foregoing, it would be desirable to provide IC memory structures with high immunity to soft errors and low cell leakage. In addition, it would be desirable to make such IC memory structures relatively small in size.